0
Research Papers

Development of Highly Efficient Combined Polishing Method for Single-Crystal Silicon Carbide

[+] Author and Article Information
Tsuneo Kurita

National Institute of Advanced Industrial
Science and Technology (AIST),
AIST Tsukuba East 1-2-1 Namiki,
Tsukuba 305 8564, Ibaraki, Japan
e-mail: t.kurita@aist.go.jp

Koji Miyake

National Institute of Advanced Industrial
Science and Technology (AIST),
AIST Tsukuba East 1-2-1 Namiki,
Tsukuba 305 8564, Ibaraki, Japan
e-mail: koji-miyake@aist.go.jp

Kenji Kawata

National Institute of Advanced
Industrial Science and Technology (AIST),
AIST Tsukuba East 1-2-1 Namiki,
Tsukuba 305 8564, Ibaraki, Japan
e-mail: ke-kawata@aist.go.jp

Kiwamu Ashida

National Institute of Advanced
Industrial Science and Technology (AIST),
AIST Tsukuba East 1-2-1 Namiki,
Tsukuba 305 8564, Ibaraki, Japan
e-mail: ashida.k@aist.go.jp

Tomohisa Kato

National Institute of Advanced
Industrial Science and Technology (AIST),
AIST Tsukuba East 1-2-1 Namiki,
Tsukuba 305 8564, Ibaraki, Japan
e-mail: t-kato@aist.go.jp

Contributed by the Manufacturing Engineering Division of ASME for publication in the JOURNAL OF MICRO- AND NANO-MANUFACTURING. Manuscript received December 14, 2016; final manuscript received May 16, 2017; published online June 7, 2017. Assoc. Editor: Cheryl Xu.

J. Micro Nano-Manuf 5(3), 031004 (Jun 07, 2017) (5 pages) Paper No: JMNM-16-1072; doi: 10.1115/1.4036828 History: Received December 14, 2016; Revised May 16, 2017

The aim of this research is to develop a combined polishing technology for single-crystal silicon carbide (SiC) wafers, which is known to be difficult to process due to its high hardness. This paper proposes a combined polishing method based on converting SiC into a material with a relatively low hardness and then polishing this material using abrasive particles with a higher hardness. An electrochemical technique was tried to reduce the hardness of SiC. The effectiveness of the combined technique is experimentally demonstrated. In addition, the temporal changes of the thickness of SiO2 layer and the relationship between the electrochemical machining current and the thickness of SiO2 layer are shown.

FIGURES IN THIS ARTICLE
<>
Copyright © 2017 by ASME
Your Session has timed out. Please sign back in to continue.

References

Figures

Grahic Jump Location
Fig. 1

Experimental apparatus image in the ECM method

Grahic Jump Location
Fig. 2

Wafer surface before and after ECM: (a) before ECM and (b) after ECM

Grahic Jump Location
Fig. 3

XPS measurement results before and after ECM

Grahic Jump Location
Fig. 4

Experimental setup for complex machining

Grahic Jump Location
Fig. 5

Complex machining results

Grahic Jump Location
Fig. 6

Surface profile along the dotted line (α–α′) in Fig. 5

Grahic Jump Location
Fig. 7

Schematic of the experimental apparatus used in multipoint machining

Grahic Jump Location
Fig. 8

Experimental apparatus for multipoint machining: A, liquid container; B, waterproof seal; C, SiC wafer; D, conduction paid; E, electrode

Grahic Jump Location
Fig. 9

Multipoint complex machining results

Grahic Jump Location
Fig. 10

Surface profile along the dotted line (β–β′) in Fig. 9

Grahic Jump Location
Fig. 11

Relationship between the thickness of SiO2 layer and ECM time

Grahic Jump Location
Fig. 12

Relationship between the processing current and processing state associated with changes in the balance of the strength of ECM and polishing

Grahic Jump Location
Fig. 13

Relationship between ECM current and thickness of SiO2 layer

Tables

Errata

Discussions

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In