0
Research Papers

Design of Tool for Exfoliation of Monocrystalline Microscale Silicon Films

[+] Author and Article Information
Martin Ward

Department of Mechanical Engineering,
University of Texas at Austin,
204 East Dean Keeton Street,
Austin, TX 78712-1591
e-mail: mjward@utexas.edu

Michael Cullinan

Department of Mechanical Engineering,
University of Texas at Austin,
204 East Dean Keeton Street,
Austin, TX 78712-1591
e-mail: michael.cullinan@austin.utexas.edu

1Corresponding author.

Contributed by the Manufacturing Engineering Division of ASME for publication in the JOURNAL OF MICRO-AND NANO-MANUFACTURING. Manuscript received December 15, 2018; final manuscript received March 30, 2019; published online May 15, 2019. Editor: Nicholas Fang.

J. Micro Nano-Manuf 7(1), 011003 (May 15, 2019) (7 pages) Paper No: JMNM-18-1067; doi: 10.1115/1.4043420 History: Received December 15, 2018; Revised March 30, 2019

This paper presents the development of a prototype exfoliation tool and process for the fabrication of thin-film, single crystal silicon, which is a key material for creating high-performance flexible electronics. The process described in this paper is compatible with traditional wafer-based, complementary metal–oxide–semiconductor (CMOS) fabrication techniques, which enables high-performance devices fabricated using CMOS processes to be easily integrated into flexible electronic products like wearable or internet of things devices. The exfoliation method presented in this paper uses an electroplated nickel tensile layer and tension-controlled handle layer to propagate a crack across a wafer while controlling film thickness and reducing the surface roughness of the exfoliated devices as compared with previously reported exfoliation methods. Using this exfoliation tool, thin-film silicon samples are produced with a typical average surface roughness of 75 nm and a thickness that can be set anywhere between 5 μm and 35 μm by changing the exfoliation parameters.

FIGURES IN THIS ARTICLE
<>
Copyright © 2019 by ASME
Your Session has timed out. Please sign back in to continue.

References

Ying, M. , Bonifas, A. P. , Lu, N. , Su, Y. , Li, R. , Cheng, H. , Ameen, A. , Huang, Y. , and Rogers, J. A. , 2012, “ Silicon Nanomembranes for Fingertip Electronics,” Nanotechnology, 23(34), p. 344004. [CrossRef] [PubMed]
Kim, J. , Lee, M. , Shim, H. J. , Ghaffari, R. , Cho, H. R. , Son, D. , Jung, Y. H. , Soh, M. , Choi, C. , Jung, S. , Chu, K. , Jeon, D. , Lee, S.-T. , Kim, J. H. , Choi, S. H. , Hyeon, T. , and Kim, D.-H. , 2014, “ Stretchable Silicon Nanoribbon Electronics for Skin Prosthesis,” Nat. Commun., 5, p. 5747. [CrossRef] [PubMed]
Hussain, A. M. , and Hussain, M. M. , 2016, “ CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications,” Adv. Mater., 28(22), pp. 4219–4249. [CrossRef] [PubMed]
Pang, C. , Lee, C. , and Suh, K.-Y. , 2013, “ Recent Advances in Flexible Sensors for Wearable and Implantable Devices,” J. Appl. Polym. Sci., 130(3), pp. 1429–1441. [CrossRef]
Fortunato, E. , Barquinha, P. , and Martins, R. , 2012, “ Oxide Semiconductor Thin-Film Transistors: A Review of Recent Advances,” Adv. Mater., 24(22), pp. 2945–2986. [CrossRef] [PubMed]
Sirringhaus, H. , 2014, “ 25th Anniversary Article: Organic Field-Effect Transistors: The Path Beyond Amorphous Silicon,” Adv. Mater., 26(9), pp. 1319–1335. [CrossRef] [PubMed]
Takei, K. , Takahashi, T. , Ho, J. C. , Ko, H. , Gillies, A. G. , Leu, P. W. , Fearing, R. S. , and Javey, A. , 2010, “ Nanowire Active-Matrix Circuitry for Low-Voltage Macroscale Artificial Skin,” Nat. Mater., 9(10), pp. 821–826.
Chaney, R. L. , Hackler, D. R. , Wilson, D. G. , and Meek, B. N. , 2014, “ Physically Flexible High Performance Single Crystal CMOS Integrated with Printed Electronics,” IEEE Workshop On Microelectronics And Electron Devices (WMED), Boise, ID, Apr. 18, pp. 1–4.
Hackler, D. R. , and Chaney, R. L. , 2015, “ Semiconductor on Polymer Substrate,” U.S. Patent No. US9082881B1.
Bruel, M. , 1998, “ The History, Physics, and Applications of the Smart-Cut® Process,” MRS Bull., 23(12), pp. 35–39. [CrossRef]
Henley, F. , Kang, S. , Liu, Z. , Tian, L. , Wang, J. , and Chow, Y.-L. , 2009, “ Beam-Induced Wafering Technology for Kerf-Free Thin PV Manufacturing,” 34th IEEE Photovoltaic Specialists Conference (PVSC), Philadelphia, PA, June 7–12, p. 001718.
Thouless, M. D. , Evans, A. G. , Ashby, M. F. , and Hutchinson, J. W. , 1987, “ The Edge Cracking and Spalling of Brittle Plates,” Acta Metall., 35(6), pp. 1333–1341. [CrossRef]
Tanielian, M. , Lajos, R. E. , and Blackstone, S. , 1986, “ Method of Making Thin Free Standing Single Crystal Films,” U.S. Patent No. US4582559A.
Dross, F. , Robbelein, J. , Vandevelde, B. , Van Kerschaver, E. , Gordon, I. , Beaucarne, G. , and Poortmans, J. , 2007, “ Stress-Induced Large-Area Lift-Off of Crystalline Si Films,” Appl. Phys. A, 89(1), pp. 149–152. [CrossRef]
Rao, R. A. , Mathew, L. , Saha, S. , Smith, S. , Sarkar, D. , Garcia, R. , Stout, R. , Gurmu, A. , Onyegam, E. , and Ahn, D. , 2011, “ A Novel Low Cost 25 μm Thin Exfoliated Monocrystalline Si Solar Cell Technology,” 37th IEEE Photovoltaic Specialists Conference (PVSC), Seattle, WA, June 19–24, p. 001504.
Mathew, L. , and Jawarani, D. , 2010, “ Method of Forming an Electronic Device Using a Separation-Enhancing Species,” U.S. Patent No. US7749884B2.
Zhai, Y. , Mathew, L. , Rao, R. , Xu, D. , and Banerjee, S. K. , 2012, “ High-Performance Flexible Thin-Film Transistors Exfoliated From Bulk Wafer,” Nano Lett., 12(11), pp. 5609–5615. [CrossRef] [PubMed]
Bedell, S. W. , Fogel, K. , Lauro, P. , Shahrjerdi, D. , Ott, J. A. , and Sadana, D. , 2013, “ Layer Transfer by Controlled Spalling,” J. Phys. D: Appl. Phys., 46(15), p. 152002. [CrossRef]
Bedell, S. W. , Shahrjerdi, D. , Hekmatshoar, B. , Fogel, K. , Lauro, P. A. , Ott, J. A. , Sosa, N. , and Sadana, D. , 2012, “ Kerf-Less Removal of Si, Ge, and III–V Layers by Controlled Spalling to Enable Low-Cost PV Technologies,” IEEE J. Photovolt., 2(2), pp. 141–147. [CrossRef]
Bedell, S. W. , Shahrjerdi, D. , Fogel, K. , Lauro, P. , Hekmatshoar, B. , Li, N. , Ott, J. , and Sadana, D. K. , 2013, “ Cost-Effective Layer Transfer by Controlled Spalling Technology,” ECS Trans., 50(7), pp. 315–323. [CrossRef]
Shahrjerdi, D. , and Bedell, S. W. , 2013, “ Extremely Flexible Nanoscale Ultrathin Body Silicon Integrated Circuits on Plastic,” Nano Lett., 13(1), pp. 315–320. [CrossRef] [PubMed]
Shahrjerdi, D. , Bedell, S. W. , Khakifirooz, A. , Fogel, K. , Lauro, P. , Cheng, K. , Ott, J. A. , Gaynes, M. , and Sadana, D. K. , 2012, “ Advanced Flexible CMOS Integrated Circuits on Plastic Enabled by Controlled Spalling Technology,” IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 10–13, pp. 5.1.1–5.1.4.
Schönfelder, S. , Breitenstein, O. , Rissland, S. , De Donno, R. , and Bagdahn, J. , 2012, “ Glue-Cleave: Kerfless Wafering for Silicon Wafers With Metal on Glueing and Removable Interface,” 22nd Workshop on Crystalline Silicon Solar Cells and Modules: Materials and Processes, Vail, CO, July 22–25.
Serra, J. , Bellanger, P. , Bouchard, P. O. , and Bernacki, M. , 2014, “ Room Temperature Kerfless Silicon Thin Foils Obtained Via a Stress Inducing Epoxy Layer: Room Temperature Kerfless Silicon Thin Foils Obtained Via a Stress Inducing Epoxy Layer,” Phys. Status Solidi (c), 11(11–12), pp. 1644–1647. [CrossRef]
Hensen, J. , Niepelt, R. , Kajari-Schroder, S. , and Brendel, R. , 2015, “ Directional Heating and Cooling for Controlled Spalling,” IEEE J. Photovolt., 5(1), pp. 195–201. [CrossRef]
Niepelt, R. , Hensen, J. , Steckenreiter, V. , Brendel, R. , and Kajari-Schöder, S. , 2015, “ Kerfless Exfoliated Thin Crystalline Si Wafers With Al Metallization Layers for Solar Cells,” J. Mater. Res., 30 (21), pp. 3227–3240. [CrossRef]
Suo, Z. , and Hutchinson, J. W. , 1989, “ Steady-State Cracking in Brittle Substrates Beneath Adherent Films,” Int. J. Solids Struct., 25(11), pp. 1337–1353. [CrossRef]
Drory, M. D. , Thouless, M. D. , and Evans, A. G. , 1988, “ On the Decohesion of Residually Stressed Thin Films,” Acta Metall., 36(8), pp. 2019–2028. [CrossRef]
Ward, M. , and Cullinan, M. , 2019, “ A Fracture Model for Exfoliation of Thin Silicon Films,” Int. J. Fract. (epub).
Tanaka, M. , Higashida, K. , Nakashima, H. , Takagi, H. , and Fujiwara, M. , 2006, “ Orientation Dependence of Fracture Toughness Measured by Indentation Methods and Its Relation to Surface Energy in Single Crystal Silicon,” Int. J. Fract., 139(3–4), pp. 383–394. [CrossRef]
Janssen, G. C. A. M. , Abdalla, M. M. , van Keulen, F. , Pujada, B. R. , and van Venrooy, B. , 2009, “ Celebrating the 100th Anniversary of the Stoney Equation for Film Stress: Developments From Polycrystalline Steel Strips to Single Crystal Silicon Wafers,” Thin Solid Films, 517(6), pp. 1858–1867. [CrossRef]
Ward, M. , 2018, “ Wafer Scale Exfoliation of Monocrystalline Micro-Scale Silicon Films,” Master's thesis, The University of Texas at Austin, Austin, TX.

Figures

Grahic Jump Location
Fig. 1

Spontaneous exfoliation of a silicon thin film showing poor uniformity and surface finish

Grahic Jump Location
Fig. 2

Image of the wedge-type exfoliation tool and diagram of the wedge mechanism. The wedge pries the crack open but does not reach the crack tip.

Grahic Jump Location
Fig. 3

Controlled peeling concept diagram. Rollers move the tensioned handle film over the wafer to exfoliate the film.

Grahic Jump Location
Fig. 4

Prototype controlled peeling tool CAD rendering

Grahic Jump Location
Fig. 5

Prototype controlled peeling tool

Grahic Jump Location
Fig. 6

Close-up of exfoliation process and silicon thin-film

Grahic Jump Location
Fig. 7

(a) Sample test result at approximately 20 μm Si film thickness, (b) bend radius demonstration, and (c) sample film thickness map

Grahic Jump Location
Fig. 8

Roughness comparison: (Top) White light interferometer measurements of each method and (bottom) photographs of each sample. Note regular ridges on the wedge tool sample and irregular ridges on the hand peeled sample.

Grahic Jump Location
Fig. 9

Example wafer measurement and prediction profile demonstrating crack depth control with step change

Grahic Jump Location
Fig. 10

Example wafer measurement and prediction profile targeting minimum thickness aided by metamodel prediction

Tables

Errata

Some tools below are only available to our subscribers or users with an online account.

Related Content

Customize your page view by dragging and repositioning the boxes below.

Related Journal Articles
Related eBook Content
Topic Collections

Sorry! You do not have access to this content. For assistance or to subscribe, please contact us:

  • TELEPHONE: 1-800-843-2763 (Toll-free in the USA)
  • EMAIL: asmedigitalcollection@asme.org
Sign In